1. Field of the Invention
The present invention relates to a digital/analog converter, in which a divided-voltage storing section and divided-voltage selecting section are added in a conventional digital/analog converter which processes a digital signal with an 8-bit resolution, so that a digital signal with a high resolution of more than 10 bits can be processed, the size of an IC on which the digital/analog converter is mounted can be reduced by miniaturizing the digital/analog converter, and a desired voltage can be output quickly.
2. Description of the Related Art
In general, a digital/analog converter converts a digital quantity into a corresponding analog quantity. During image sensing, the digital/analog converter determines the range of digital data which is stored according to the brightness of an image, when a user inputs a digital control code. Then, the digital/analog converter converts the digital data into an analog signal.
As a widely-used digital/analog converter, there are generally provided a converter using a resistor array, a converter using a capacitor, a converter using a current cell and the like.
In such digital/analog converters according to the related art, as the number of bits of an input signal increases, the overall area of the circuit significantly increases. In the case of the converter using a resistor array, if the number of bits of an input signal increases from 8 to 10, the number of resistors which are required for the digital/analog conversion significantly increases from 256(28) to 1024(210). The number of switches which are accordingly needed also increases significantly. Such an increase of two bits causes the overall area of the digital/analog converter to increase four times. Such an increase in area also occurs in other digital/analog converters. Further, when a semiconductor is manufactured, an increase in the area of a circuit means an increase in cost. Therefore, in order to design a low-cost digital/analog converter, a digital/analog converter with a new structure is required, of which the overall circuit area does not increase despite an increase in the number of bits of an input signal.
FIG. 1 is a block diagram illustrating the construction of a digital/analog converter which processes a digital signal with an 8-bit resolution according to the related art.
As shown in FIG. 1, the conventional digital/analog converter which processes a digital signal with an 8-bit resolution is composed of a divided-voltage generating section 101 which divides a reference supply voltage VDD through the voltage distribution, a decoder section 103 which receives a digital signal so as to output a decoded selection signal, a first divided-voltage selecting section 102 which selects and outputs a plurality of divided-voltages among the divided-voltages generated from the first divided-voltage generating section 101 on the basis of the output selection signal, a second divided-voltage selecting section 104 which selects and outputs a plurality of divided-voltages among the divided-voltages output from the first divided-voltage selecting section on the basis of the output selection signal, and a voltage output section 105 which outputs a predetermined voltage selected by the second divided-voltage selecting section.
The first divided-voltage generating section 101 is composed of 256(28) or 257(28+1) resistors which are serially connected. One end thereof receives the reference supply voltage VDD, and the other end thereof is connected to the ground GND of the circuit. Further, predetermined divided-voltages VR1 to VR256 are respectively output from the connection points between the resistors R0 to R256, that is, the nodes formed between the resistances of the divided-voltage generating section 101.
For example, if the connection point between the resistors R1 and R2 is set to the first node and the total resistance of 257 serially-connected resistors is referred to as Rtot, a divided-voltage VRn which is output from the Nth node can be calculated by the following equation: Vn=(R0+R1+ . . . +Rn−1)/Rtot×VDD (n is in the range of 1 to 256).
The first divided-voltage selecting section 102 is provided with 256 switches S/W1 to S/W256. The switches S/W1 to S/W256 are respectively connected to the nodes formed in the first divided-voltage generating section 101.
The first divided-voltage selecting section 102 selects and outputs 16 divided-voltages among the 256 divided-voltages generated by the divided-voltage generating section 101 on the basis of the selection signal output from the decoder section 103 which will be described below.
The second divided-voltage selecting section 104 is provided with 16 switches S/W1a to S/W16a. The 16 switches S/W1a to S/W16a are respectively connected to 16 nodes selected by the first divided-voltage selecting section 102, among the nodes formed in the divided-voltage generating section 101.
Therefore, the second divided-voltage selecting section 104 selects and outputs one desired voltage among 16 divided-voltages selected by the first divided-voltage selecting section 102 on the basis of the selection signal output from the decoder section 103.
The decoder section 103 receives an 8-bit digital signal from outside. The decoder section 103 is composed of a first decoder 103a which decodes four higher-order bits of the 8-bit digital signal output from outside so as to output a decoded selection signal and a second decoder 103b which decodes four lower-order bits thereof so as to output a decoded selection signal.
The first divided-voltage selecting section 102 first selects 16 divided-voltages among the 256 divided-voltages generated from the first divided-voltage generating section 101 on the basis of the selection signal output from the first decoder 103a. 
The second divided-voltage selecting section 104 selects one desired voltage among 16 divided-voltages selected by the first divided-voltage selecting section 102 on the basis of the selection signal output from the second decoder 103b. 
The voltage output section 105 is composed of an output buffer 105a which buffers and outputs one voltage selected by the second divided-voltage selecting section 104.
Therefore, the voltage selected by the second divided-voltage selecting section 104 is output to an output terminal through the output buffer 105a. Accordingly, an analog output voltage corresponding to the 8-bit digital signal output from outside is output through the output terminal of the digital/analog converter which processes a digital signal with an 8-bit resolution.
FIG. 2 is a block diagram illustrating the construction of a conventional digital/analog converter which processes a digital signal with a 10-bit resolution.
As shown in FIG. 2, the conventional digital/analog converter, which processes a digital signal with a 10-bit resolution, is composed of a first divided-voltage generating section 201 which divides a reference supply voltage through the voltage distribution, a decoder section 203 which receives a digital signal so as to output a decoded selection signal, a first divided-voltage selecting section 202 which selects and outputs a plurality of divided-voltages among the divided-voltages generated from the first divided-voltage generating section 201 on the basis of the output selection signal, a second divided-voltage selecting section 204 which selects and outputs a plurality of divided-voltages among the divided-voltages output from the first divided-voltage selecting section on the basis of the output selection signal, and a voltage output section 205 which outputs predetermined voltages selected from the second divided-voltage selecting section.
Different from the first divided-voltage generating section 101 of FIG. 1, the first divided-voltage generating section 201 is composed of 1024(210) or 1025(210+1) resistors which are serially connected, because the digital/analog converter processes a digital signal with 10-bit resolution. One end thereof receives the reference supply voltage VDD, and the other end thereof is connected to the ground GND of the circuit. Further, predetermined divided-voltages VR1 to VR1024 are respectively output from the connection points between the resistors R0 to R1024, that is, the nodes formed between the respective resistors of the first divided-voltage generating section 201.
For example, if the connection point between the resistors R1 to R2 is set to the first node and the total resistance of 1025 serially-connected resistors is referred to as Rtot, a divided-voltage VRn which is output from the Nth node can be calculated by the following equation: Vn=(R0+R1+ . . . +Rn−1)/Rtot×VDD (n is in the range of 1 to 1024).
Different from the first divided-voltage selecting section 102 of FIG. 1, the first divided-voltage selecting section 202 is provided with 1024 switches S/W1 to S/W1024. The switches S/W1 to S/W1024 are respectively connected to the nodes formed in the divided-voltage generating section 201.
The first divided-voltage selecting section 202 selects and outputs 32 divided-voltages among 1024 divided-voltages generated by the divided-voltage generating section 201 on the basis of a selection signal output from the decoder section 203 which will be described below.
The second divided-voltage selecting section 204 is provided with 32 switches S/W1a to S/W32a. The 32 switches S/W1a to S/W32a are respectively connected to 32 nodes which are selected by the first divided-voltage selecting section 202 among the nodes formed in the divided-voltage generating section 201.
The second divided-voltage selecting section 204 selects and outputs one desired voltage among 32 divided voltages selected by the first divided-voltage selecting section 202 on the basis of the selection signal output from the decoder section 203.
The decoder section 203 receives a 10-bit digital signal from the outside. The decoder section 203 is composed of a first decoder 203a which decodes five higher-order bits of the 10-bit digital signal output from outside so as to output a decoded selection signal and a second decoder 203b which decodes five lower-order bits thereof so as to output a decoded selection signal.
Therefore, the first divided-voltage selecting section 202 first selects 32 divided-voltages among 1024 divided-voltages generated from the first divided-voltage generating section 201 on the basis of the selection signal output from the first decoder 203a. 
The second divided-voltage selecting section 204 selects one desired voltage among 32 divided-voltages selected from the first divided-voltage selecting section 202 on the basis of the selection signal output from the second decoder 203b. 
The voltage output section 205 is composed of an output buffer 205a which buffers and outputs one voltage selected by the second voltage selecting section 204.
The voltage selected by the second divided-voltage selecting section 204 is output to an output terminal through the output buffer 205a. Accordingly, the output voltage of an analog signal corresponding to the 10-bit digital signal input from outside is output through the output terminal of the digital/analog converter which processes a digital signal with a 10-bit resolution.
However, in the conventional digital/analog converter which processes a digital signal with an 8-bit resolution as described above, there are provided the divided-voltage generating sections and divided-voltage selecting sections which are suitable for processing a digital signal with an 8-bit resolution. Therefore, it is impossible to process a digital signal with high resolution of more than 10 bits.
Further, in the conventional digital/analog converter which processes a digital signal with a 10-bit resolution as described above, high resolution of more than 10 bits can be obtained. However, since the number of resistors composing the divided-voltage generating section and switches composing the divided-voltage selecting section increases, the area of the circuit also increases.
Furthermore, in the conventional digital/analog converter which processes a digital signal with an 8-bit and 10-bit resolution as described above, a desired voltage cannot be output quickly because of the influence of a parasitic capacitor which is present in a switch or the like.